1. Field of the Invention
This invention relates to a semiconductor memory device with electrically rewritable and non-volatile memory cells, i.e., EEPROM, and specifically to a technology for reducing the write error rate of a NAND-type flash memory.
2. Description of the Related Art
A NAND-type flash memory is known as high integrality one in electrically rewritable and non-volatile semiconductor memories (EEPROMs). In the NAND-type flash memory, a plurality of memory cells are connected in series in such a manner that adjacent two memory cells share a source/drain diffusion layer to constitute a NAND cell unit. The both ends of the NAND cell unit are coupled to a bit line and a source line via select gate transistors, respectively. With such the NAND cell unit structure, the NAND-type flash may be formed to have a smaller unit cell area than that of a NOR-type flash memory, and have a large capacity.
A memory cell in the NAND-type flash memory has a floating gate (i.e., charge storage layer) formed above a semiconductor substrate with a tunnel insulating film interposed therebetween and a control gate stacked above the floating gate with a gate insulating film interposed therebetween so as to store data in a non-volatile manner defined by a charge storage state in the floating gate. Explaining in detail, binary data storage will be defined as follows: an electron-injected state of the floating gate, i.e., a high threshold voltage state, is referred to as, for example, data “0” while an electron-discharged state of the floating gate, i.e., a low threshold state, is referred to as data “1”. Recently, multi-level data storage schemes such as four-level data storage schemes tend to be adapted to the NAND-type flash memory by sub-dividing the threshold distributions.
Data write in the NAND-type flash memory is performed page by page where a page is defined by a set of memory cells arranged along a selected word line (or a half thereof). Explaining in detail, data write is performed to inject electrons into the floating gate from the cell channel by FN tunneling with applying write voltage Vpgm to a selected word line. In this case, a NAND cell channel will be controlled in potential in accordance with write data “1” or “0” applied to the cell channel via to a selected bit line. This will be explained as follows.
In case of “0” write, Vss is applied to a bit line, and it is transferred to a selected cell's channel via a turned on select gate transistor. At this time, a large electric field is applied between the floating gate and the channel in the selected cell, so that electrons are injected into the floating gate. By contrast, in case of “1” write, Vdd is applied to a bit line. Therefore, the NAND cell channel is charged up to Vdd-Vth (Vth is threshold voltage of the select gate transistor) to be set in a floating state. At this time, the selected cell's channel is boosted by capacitive coupling from a selected word line, and electron injection into the floating gate will be inhibited.
If the cell channel boost is not sufficient in a “1” write cell (i.e., write-inhibited cell) with Vpgm applied, electron injection into the floating gate occurs, and it leads to an undesirable threshold voltage change. Non-selected word lines are usually applied with a write pass voltage Vpass set to be lower than the write voltage Vpgm, so that a “1” write cell's channel is boosted and electron injection into the floating gate is inhibited. If, in these non-selected cells, the cell channel boost is insufficient, erroneous writes often occur.
Conventionally, there have been provided some channel voltage control schemes used in a write or program mode, which are able to prevent “1” write cells and non-selected cells in a NAND-type flash memory from being erroneously written, as follows (refer to, for example, JP-A-2004-185690).
(1) Self-Boost (SB) scheme: at a “1” write time, all channels in a NAND cell unit are set in a floating state to be boosted by capacitive coupling from a selected word line with Vpgm applied. Except the selected word line, all non-selected word lines are applied with a write pass voltage Vpass lower than Vpgm.
(2) Local Self-Boost (LSB) scheme: at a “1” write time, a selected cell's channel is isolated from others to be boosted. This is on the assumption that memory cells in a NAND cell unit are sequentially written from one on the source line side. Two non-selected word lines disposed adjacent to a selected word line are applied with a channel isolating voltage Viso (<Vpass); and the remaining non-selected word lines with a medium voltage (pass voltage) Vpass.
(3) Erase Area Self-Boost (EASB) scheme: at a “1” write time, written cells' channel area and unwritten cells' channel area including a selected cell are isolated from each other and boosted independently. This also is on the assumption that memory cells in a NAND cell unit are sequentially written from one on the source line side. A non-selected word line, which is located on the source line side of a selected word line and adjacent to it, is applied with channel isolating voltage Viso sufficiently lower than Vpass, so that two channel areas are isolated from each other and boosted.
Even if either one of these channel voltage control schemes is adapted, in case miniaturization of a NAND-type flash memory is further enhanced, such a matter remains to be solved that erroneous write occurs in non-selected cells adjacent to select gate transistors (specifically the source line side select gate transistor). At a data write time, the source line side select gate transistor is kept off with gate voltage 0V. Therefore, when the non-selected cell adjacent to the select gate transistor is applied with pass voltage Vpass, gate-induced drain leakage (GIDL) current is generated at the drain edge of the select gate transistor, and such an erroneous write occurs in the non-selected cell that electrons are injected into the floating gate due to the GIDL current (refer to, for example, Jae-Duk Lee et al, “A NEW PROGRAMMING DISTURBANCE IN NAND FLASH MEMORY BY SOURCE/DRAIN HOT-ELECTRONS GENERATED BY GIDL CURRENT”, NVSMW2006, p. 31-33). It is known that the same erroneous write occurs in the non-selected cell adjacent to the bit line side select gate transistor as above-described case.
The above-described error write stress in the cells adjacent to the select gate transistors will also be generated in such a case that these cells are “1” write cells with Vpgm applied. However, write stress applied to the “1” write cell is only once when a corresponding page is selected. By contrast, error write stress to the adjacent non-selected cell with write pass voltage Vpass applied will be applied in all cases that other pages are selected in the same NAND cell block. Therefore, the error write stress due to the write pass voltage Vpass becomes a matter.
To suppress the erroneous write due to GIDL current, it may be effective somewhat to dispose a dummy cell adjacent to the select gate transistor, which does not serve for storing data. The above-described dummy cell scheme has been provided as such a technology that reduces the position dependence of write/erase property of memory cells to equalize data states in the NAND cell unit (for example, refer to JP-A-2004-127346).
However, even if the above-described dummy cell scheme is adapted, in a further miniaturized NAND-type flash memory with a design rule such as 60 nm or less, the erroneous write due to GIDL current remains a matter.